N. Martínez Madrid, Virtual Component Reuse for Future Analog/Mixed-Signal Design, Forum on Design Languages (FDL,) SIG-VHDL & ECSI, Tübingen, 2000.
R. Seepold, N. Martínez Madrid, „Hardware/Software Co-Design for IP Objects based on CORBA,“ Proc. VIUF Fall, Editorial: IEEE Press, ISBN: 0-7695-0465-5, p. 63-68, Orlando, October 1999.
A. Alonso, L. Sánchez, A. Groba, S. Pickin, N. Martínez Madrid, J.A. de la Puente, Development of Computer Control Systems with Hardware-Software Codesign, 14th World Congress of Int. Federation of Automatic Control, IFAC'99, 1999.
N. Martínez Madrid, J.P. Bowen, R. France, M. Larrondo Petrie, C. Delgado Kloos, P.T. Breuer, Reasoning about VHDL and VHDL-AMS using Denotational Semantics, Design, Automation and Test in Europe (DATE), IEEE Press, 1999.
N. Martínez Madrid, J.P.Bowen, R.France, M.Larrondo Petrie, C. Delgado Kloos, P.T. Breuer, A core language and simple formal denotational semantics for VHDL-AMS, IEEE/VIUF Int'l Wshp on Behavioral Modeling and Simulation (BMAS), Orlando, 1998.
N. Martínez Madrid, P.T. Breuer, C. Delgado Kloos, A Semantic Model for VHDL-AMS, IFIP Conference on Correct Hardware Design and Verification Methods CHARME '97, Chapman Hall, 1997.
L. Sánchez , C. Delgado Kloos, N. Martínez Madrid, A. Marín López, Especificación de aspectos no funcionales de sistemas hardware-software, V Jornadas de Concurrencia, Vigo, 1997.
P.T. Breuer, N. Martínez Madrid, L. Sánchez Fernández, A. Marín López, C. Delgado Kloos, A Refinement Calculus for VHDL, EuroDAC '96, IEEE Computer Society Press , 1996.
P.T. Breuer, N. Martínez Madrid, L. Sánchez Fernández, A. Marín López, C. Delgado Kloos, A Formal Method for Specification and Refinement of Real-Time Systems, VIII EuroMicroWorkshop on Real Time Systems, IEEE Computer, 1996.
C. Carreras, J.C. López, M.L. López, C. Delgado Kloos, N. Martínez Madrid, L. Sánchez, A Co-Design Methodology Based on Formal Specification and High-level Estimation, 4th International Workshop on Hardware/Software Co-Design (CODES/CASHE'96) , IEEE Computer, 1996.
P.T. Breuer, N. Martínez Madrid, C. Delgado Kloos et. al., A Process Algebra for VHDL with Signal Attributes, 3rd Asia Pacific Conference on Hardware Description Languages, APCHDL '96, IFIP WG 10.5, Bangalore, 1996.
P.T. Breuer, N. Martínez Madrid, C. Delgado Kloos et. al, Putting Logical Time into a Real-Time Language, 3rd Asia Pacific Conference on Hardware Description Languages, APCHDL '96, IFIP WG 10.5, Bangalore, 1996.
P.T. Breuer, J. Bowen, N. Martínez Madrid, C. Delgado Kloos et. al., Just in Time - A Specification Calculus for Real Time Systems, Software Engineering Research Forum, Boca Raton, 1995.
P.T. Breuer and N. Martínez Madrid, A Native Process Algebra forVHDL, EuroDAC with EuroVHDL '95, IEEE Press, 1995.
N. Martínez Madrid, A. Marín López, S. Deprés Díaz, C. Delgado Kloos and L. Sánchez Fernández, Cremalleras y espirales o cómo co-diseñar mejor, I Jornadas de Informática, Puerto de la Cruz, 1995.
P.T. Breuer, N. Martínez Madrid, A. Marín López, L. Sánchez Fernández and C. Delgado Kloos, Tiempo Lógico en un Lenguaje de Tiempo Real, I Jornadas de Informática, Puerto de la Cruz, 1995.
C. Delgado Kloos, N. Martínez Madrid and L. Sánchez Fernández, Hardware/Software Codesign based on LOTOS, IV Jornadas de Concurrencia, El Escorial, 1995.
C. Carreras, J.C. López, M.L. López, C. Delgado Kloos, N. Martínez Madrid and L. Sánchez, Estimation Methodology for HW-SW Codesign based on Intermediate Analytic Models, 21st CAVE, CAD for VLSI in Europe Workshop, 1994.